Conditional constructs, such “if-then” and “if-then-else” are commonly used in programming to control the sequence of instruction execution. Such constructs are typically implemented using conditional jump or branch instructions. In pipelined processors jump and branch instructions can cause control hazards. That is, immediately after the jump or branch instruction enters the execution pipeline, subsequent instructions are not executed. Instead, a condition specified by the jump or branch instruction is evaluated (to determine whether to redirect program flow) and if the condition is satisfied, then the instruction at a destination address specified by the jump or branch instruction is fetched. Depending on the system architecture (pipeline depth, instruction bus/memory latency) the number of cycles the pipeline is stalled to resolve the hazard can vary. Stalling reduced processor performance.
Because many if-then and if-then-else instruction sequences include only a few instructions per branch, a pre-fetch buffer that contains instructions fetched in advance serves as a way to reduce the stall cycles caused by conditional constructs. If the target instruction of a branch or jump has been pre-fetched, the target instruction can be read from the pre-fetch buffer instead of fetching the instruction from memory. Thus, pre-fetching can reduce the number of stall cycles associated with conditional execution and increase overall processor performance.